1. Field of the Invention
This invention relates to power switching transistors and more particularly to DMOS transistors.
2. Description of the Relevant Art
DMOS transistors of either trench or planar construction are most typically made from an array of small transistors, called "microcells" or simply "cells," connected in parallel. Each microcell has all the material layers and contacts required to make a complete transistor. The cell construction is governed by the desire to maximize the cell's perimeter (Z) for a given cell area (A), or, in other terms, the perimeter/area (Z/A) ratio. Maximization of the Z/A ratio results in the minimization of the specific on-resistance (the resistance per unit area) of the transistor, r.sub.ds(on) .times.A, defined as EQU r.sub.ds(on) .times.A=(g.sub.ds(on) /A).sup.-1, (1)
where g.sub.ds(on) is the linear region drain-source conductance.
Various microcell geometries are possible, of which the square and hexagonal microcell geometries are most frequently used. The perimeter to area Z/A ratio for either the square or the hexagonal microcells is EQU Z/A=(4a)/(a+b).sup.2, (2)
where a is the width of the silicon opening and b is the width of the trench (in a trench design) or the polysilicon (in a planar design).
FIG. 1 illustrates half a hexagonal trench microcell 5. The structure includes an n+ substrate 50, on which is grown a lightly doped n-type epitaxial layer 40. Within the epitaxial layer 40, a body region 30 of p or p+ conductivity is provided. Another n+ layer 20 overlying most of the body region 30 serves as a source region. A hexagonally shaped trench 10 is provided in the epitaxial layer and extends downward from the top surface of the cell into the epitaxial layer 40. Body region 30 is formed in epitaxial region 40 such that its deepest point is positioned below the deepest point of trench 10.
The body region 30 opens to the top surface of the epitaxial layer 40 and forms an exposed portion 60 in a horizontal cross section at the top surface of the cell. Exposed portion 60 of the body region is more heavily doped (p+) than the substantially planar remainder of the body region. The three-dimensional geometry of this hexagonal trench microcell 5 including the 120.degree. angles of the hexagonal shape improves the uniformity of the electric field in the gate oxide, compared with the uniformity of the electric field in the gate oxide of a square trench microcell, which is characterized by 90.degree. angles. The improved uniformity in the gate oxide electric field improves the gate breakdown voltage. As the angle of the microcell increases, the electric field in the gate oxide field more closely approaches that of a plane in which the uniformity of the gate oxide field is maximized. Moreover, during the process of creating the trench, the corners and sides become rounded thereby further reduce the rigidity of the angle, which, in turn, increases the uniformity of the field.
FIG. 2 shows a simplified three-dimensional representation of a square planar microcell 80. The microcell 80 includes an epitaxial layer 110 formed on a substrate 100. Also illustrated is a body region 120, a source region 130, an insulating oxide layer 140 and a source metallization layer 150. The planar microcell 80 is most typically designed in square rather than in hexagonal geometry, for computer-aided-design (CAD) convenience. Unlike the hexagonal trench structure shown in FIG. 1, a planar design, such as shown in FIG. 2, derives no benefit from the hexagonal geometry. Also, no advantage is associated with using offset cell placement (e.g. where the cells are positioned in a staggered fashion as illustrated in FIG. 2), instead of in-line cell placement (positioned in a straight line).
The hexagonal and the square cells illustrated in FIGS. 1 and 2 are usually referred to as "closed" cells. Another cell type, the "open" cell, will be later described in further detail.
The perimeter to area (Z/A) relationship given above describes a non-monotonic function of the width of the silicon opening a when the width b of the trench or the width b of the polysilicon is kept constant. This non-monotonic function has a maximum value of EQU (Z/A).sub.max =1/b, (3)
when a=b (in other words, when the width of the silicon opening a is equal to the width b of the trench in a trench design or the width b of the polysilicon in a polysilicon design).
FIG. 3 shows perimeter to area (Z/A) plots as a function of the silicon opening a and the polysilicon width b for the respective typical open and closed cells of trench and planar construction. As shown in FIG. 3, curve 301 traces the Z/A ratio versus silicon opening width a for a trench closed cell having a trench width of 2.5 .mu.m. Curve 302 traces the Z/A ratio versus silicon opening width a for a planar closed cell having a polysilicon width of 9 .mu.m. Also, curves 303-308 trace the Z/A ratio versus silicon opening width a for trench open cells (discussed later) having c.sub.1 /Z.sub.1 ratios between 0 and 0.5; the parameters c.sub.1 and Z.sub.1 are defined in FIG. 4. The circles in FIG. 3 designate the approximate state-of-the-art for the respective cell designs.
In both planar and trench designs, the dimensions of the central part of the microcell (deep-body, source implant and contact regions) are limited to the minimum size achievable with the available technology. For example, dimension a has a minimum value that is set by the lithography rules.
The perimeter (Z) of a microcell, which is defined by the gate region of the cell, is minimized in a trench design. The minimum cell perimeter Z cannot be reached in a planar design due to the JFET (junction field effect transistor) current constriction associated with such designs. Hence, under current technology, dimension b is around 2 micrometers in a trench design and from 6 to 40 micrometers in a planar design. A planar design requires a larger width because of the larger breakdown voltage specifications required.
It follows from this discussion that a trench design results in a larger perimeter to area Z/A ratio. Consequently, a trench design provides the maximum perimeter achievable with currently available technology.
FIG. 4 is an illustration of an open cell. An open cell (also called a stripe, or linear, cell) can be seen as an in-line square cell, one side of which is stretched out, such that it becomes much larger than the other side. Thus, the contributions to the Z/A ratio by the small sides are relatively insignificant, so that the Z/A ratio of an open cell can be written as: EQU Z/A=2/(a+b), (4)
which is a monotonic function of a when b are kept constant. Thus, EQU (Z/A).sub.closed-cell &gt;(Z/A).sub.open-cell when a&gt;b; (5) EQU (Z/A).sub.closed-cell &lt;(Z/A).sub.open-cell when a&lt;b. (6)
For trench DMOS transistors of all voltage specifications and for planar low-voltage DMOS transistors, the width of the silicon opening a is typically larger than the width of the trenches or polysilicon. Hence, to minimize the Z/A ratio, closed-cell designs are appropriate for trench devices of all voltage specifications. However, in a high-voltage DMOS transistor, the width of the silicon opening in a trench microcell is typically smaller than the width of the polysilicon in a planar microcell. Hence, to minimize the Z/A ratio, open-cell designs are appropriate for planar DMOS transistors that operate at high voltages.
In FIG. 4, a "modified" open cell 90 has body contacts of a predetermined width placed laterally at regular intervals and positioned perpendicular to the trenches 182. This enables lateral contact to the transistor body to occur. Unlike conventional open cells, the design of open cells 90 does not include body contacts or deep-body layers inside the cell, but have them placed laterally, at regular intervals. Also shown in FIG. 4 are parameters a, b, c.sub.1, and Z.sub.1, where a is the width of the silicon opening, b is the width of trench 182 or polysilicon, c.sub.1 is the width of the p.sup.+ region 180 provided for body contact, and Z.sub.1 is the width of the source diffusion n.sup.+ region. This design reduces dimension a, since it no longer has to accommodate the source, body, and contact line widths. In addition, from the stand point of area utilization, this design makes the open-cell construction superior to the closed-cell design. The perimeter to area Z/A ratio for this modified open cell design is given by the expression EQU Z/A=2/(a+b)!.times.1/(1+c.sub.1 /Z.sub.1)!. (7)
This function is plotted as curves 303-308 in FIG. 3, for the following c.sub.1 /Z.sub.1 ratios=0, 0.1, 0.2, 0.3, 0.4, and 0.5.
Unfortunately, full use of this perimeter to area Z/A ratio advantage cannot be made. Under the ideal design option, the use of distant body contacts (i.e. using very small c.sub.1 /Z.sub.1 ratio) ultimately leads to an open-body situation, where the source-body-drain structure forms an open-base bipolar transistor. A transistor built from these modified open cells and having distant body contacts can break down prematurely. This premature breakdown is termed "snap-back" breakdown. Hence, more closely spaced body contacts have to be provided (i.e. "snap-back" breakdown provides a lower limit constraining the ratio c.sub.1 /Z.sub.1). An increased c.sub.1 /Z.sub.1 ultimately makes the layout look similar to the one built from closed square cells.
The microcell density, also called packing density, is an alternate parameter for the characterization of the perimeter to area Z/A ratio of closed-cell designs, and is routinely measured in microcells per square inch. A state-of-the-art trench DMOS transistor built from hexagonal microcells, with a=10 .mu.m has a microcell density of 4.77.times.10.sup.6 microcells/square inch.
A higher-density process is generally considered a superior process, since it maximizes the perimeter to area Z/A ratio. Upon closer analysis, however, a large microcell density may not desirable by itself, since such density necessitates the presence of a large number of body/source contacts per unit area. In general, a higher contact density results in a lower reliability. Reliability is therefore of particular significance in a closed-cell power trench DMOS transistor, where the total number of body/source contacts per device is in the range of 100,000 to 500,000. Such a transistor supports currents in the range of 30 to 50 amperes.
In a power transistor formed by microcells, a disconnected source contact in one of the large number of microcells results not only in the loss from the total output current the contribution of the cell, a single disconnected body contact in one of the large number of microcells is enough to cause bipolar breakdown in that microcell, which, in turn, renders the transistor non-functional.
Thus, contrary to the object of a high packing density, the number of contacts per device limits minimization of the die size. Further, the range of prohibitive contact densities is reached sooner in trench designs than in planar designs, due to the small microcell sizes of trench designs. Moreover, a hexagonal microcell has an area that is 0.87 times smaller than the area of a square microcell with the same a and b dimensions. This is seen in the following equations: EQU (Area).sub.hexagonal =.sqroot.3/2!.times.(a+b).sup.2 =0.87(a+b).sup.2 ;(8) EQU (Area).sub.square =(a+b).sup.2. (9)
Therefore, to take advantage of finer lithography features, alternative microcell designs have to be considered. To maintain high reliability and yields, such alternative designs must reduce (not increase) the microcell density. In addition, such designs must not increase the specific on-resistance of the transistor. Although these requirements are apparently contradictory, they can be achieved simultaneously, since neither the packing density nor the perimeter to area Z/A ratio alone determine the specific on-resistance of a transistor.
The total on-resistance of a DMOS transistor is made up of various serially connected components, the most important of which are the channel resistance r.sub.channel, the drift resistance r.sub.drift, and the substrate resistance r.sub.sub. The total on-resistance can be described by the following equation EQU r.sub.ds(on) =r.sub.channel +r.sub.drift +r.sub.sub. (10)
The relative contributions of these components of total on-resistance can be derived from numerical two-dimensional simulations of a DMOS transistor. FIG. 5a, which is also found in the article "Trench DMOS Transistor Technology for High-Current (100 A Range) Switching," Solid State Electronics, Vol. 34 No. 5, pp. 493-507, 1991, shows computer-simulated plots of the voltage distribution along the vertical line AB running from source to drain (see FIG. 5b, which shows a cross section of a trench DMOS transistor), through the channel and drift regions, in a conventional open-cell trench DMOS transistor where a=10 .mu.m and b=2.5 .mu.m. FIG. 5a shows curves 501 and 502, being the potential distribution of two microcells having breakdown voltages of 60 V and 120 V, respectively. These transistors are each formed on top of a 400 .mu.m arsenic-doped substrate. From FIG. 5b, the contributions by the channel and drift regions to the total on-resistance of each of the DMOS transistors shown are as follows: EQU 60 V transistor: r.sub.channel =54%, r.sub.drift =35% (11) EQU 120 V transistor: r.sub.channel =23%, r.sub.drift =71% (12)
For each transistor, resistance in the substrate accounts for the remaining on-resistance of the DMOS transistor. Similar simulations for a 220 V microcell (not plotted) yield the following contribution by the channel and drift regions to the total resistance. EQU 220 V transistor: r.sub.channel =11%, r.sub.drift =87% (14)